INFO
Name: verilator
Version: 4.028-1.el8
Arch: aarch64
Summary: A fast simulator for synthesizable Verilog
License: LGPLv3 or Artistic 2.0
Vendor: Fedora Project
Build Host: buildvm-aarch64-08.arm.fedoraproject.org
Build Date: Sun Feb 16 19:19:18 2020
Size: 2457457
URL: http://www.veripool.com/verilator.html
Description: Verilator is the fastest free Verilog HDL simulator. It compiles
synthesizable Verilog, plus some PSL, SystemVerilog and Synthesis
assertions into C++ or SystemC code. It is designed for large projects
where fast simulation performance is of primary concern, and is
especially well suited to create executable models of CPUs for
embedded software design teams.
FILES
verilator-4.028.tgz
verilator.spec
REQUIRES
bison
coreutils
findutils
flex
gcc
gcc-c++
perl(Data::Dumper)
perl(Getopt::Long)
perl(IO::File)
perl(Pod::Usage)
perl(strict)
perl(vars)
perl-generators
perl-interpreter
rpmlib(CompressedFileNames) 3.0.4-1
rpmlib(FileDigests) 4.6.0-1
sed
PROVIDES
CONFIG FILES
verilator-4.028.tgz
verilator.spec s
LICENSE FILES
LGPLv3 or Artistic 2.0
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